Without limiting the scope of the invention, its background is described in connection with charge coupled device (CCD) image sensors, as an example. A typical CCD consists of several gate levels (usually polysilicon) which are used to control the potential within the silicon bulk. By applying suitable bias to the gates, the potential is modulated which in turn causes charge transfer. Virtual phase CCD was developed to minimize the number of polysilicon levels. This resulted in many advantages such as better quantum efficiency and lower dark current (elimination of surface state component of the dark current). In the virtual phase CCD one polysilicon level has been eliminated and replaced by a P+ junction. This P+ junction region is connected to the substrate through an undepleated channel stop region. Virtual phase CCD can be characterized by alternative placement of a MOS structure with JFET structures in a coupled chain. By clocking the MOS gates charge is transferred, while the JFET region potential is fixed. The potential steps which provide the necessary directionality for the charge transfer are usually created by a suitable ion implantation. It is not necessary to connect the virtual phase region to the substrate through the channel stops. Other methods are possible. See for example "Method of Making Top Buss Virtual Phase Frame Interline Transfer CCD Image Sensor", U.S. Pat. No. 5,151,380.
A CCD with no MOS gate has been developed by M. Kleefstra "First Experimental Bipolar CCD" Microelectronics, vol 7 pp. 68-69, December 1975. In this CCD the JFETS are placed side-by-side with small gaps between them. By careful control of potential profile in the gaps it is possible to achieve charge transfer and not have electrode-to-electrode shorts or large leakage currents. The control of the inter-electrode spacing, doping profile, and thus potential is crucial to this device. It is difficult to obtain a complete satisfaction of all the parameters. Improvement of this concept has been described in "Virtual Phase Buried Channel CCD", U.S. Pat. No. 4,779,124. In this structure, the virtual phase electrode remains as it existed in the virtual phase CCD. The MOS gate has been replaced by an "N+P" junction. P layer under the N+ region (gate) provides the necessary barrier to prevent the electrons from the N+ region to flow into the N type buried channel. In this structure there is no current flow from one P+ or N+ region to the other. The inter-electrode leakage and shorts have been eliminated. It is also much easier to control the potential profile between the electrodes and thus achieve smooth transitions with excellent charge transfer efficiency. The charge transfer directionality is built into the structure by a suitable ion implantation.